1. Field of the Invention
The present invention relates to carriers and fabrication methods of coreless packaging substrates, and, more particularly, to a carrier and a method for fabricating a coreless packaging substrate using the same.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. Accordingly, different types of packages, such as wire bonding or flip-chip packages, have been developed. To meet high integration and miniaturization requirements of semiconductor packages, packaging substrates are developed from single layer circuit boards to multi-layer circuit boards so as to provide more spaces for circuit layout in a limited area by using interlayer connection technologies and reduce the thickness of the packaging substrates.
A conventional packaging substrate has a core board having circuits formed thereon, and built-up structures symmetrically formed on both sides of the core board. However, the use of the core board increases the length of the conductive path and the thickness of the overall structure, and consequently does not meet high performance and miniaturization requirements of electronic products.
Accordingly, coreless packaging substrates are provided to shorten the conductive path and reduce the thickness of the overall structure.
FIGS. 1A to 1G are schematic cross-sectional views showing a conventional coreless packaging substrate and a fabrication method thereof.
Referring to FIG. 1A, a release layer 11 is formed on each of top and bottom surfaces of a carrier 10. The release layer 11 has an area smaller than that of the carrier 10. Therefore, an adhesive layer 12 is formed on a portion of the carrier 10 that is not covered by the release layer 11 such that the release layer 11 is surrounded by the adhesive layer 12. Further, a metal layer 13 is formed on the release layer 11 and the adhesive layer 12.
In another embodiment, referring to FIG. 1A′, an adhesive layer 12 is formed on each of top and bottom surfaces of a carrier 10. Further, a release layer 11 having an area smaller than that of the carrier 10 is attached to the adhesive layer 12 in a manner that the release layer 11 is surrounded by the adhesive layer 12. Thereafter, a metal layer 13 is formed on the release layer 11 and the adhesive layer 12.
Referring to FIG. 1B, continued from FIG. 1A, a base circuit layer 14 is formed on the metal layer 13 at the top side of the carrier 10, and a built-up structure 15 is formed on the metal layer 13 and electrically connected to the base circuit layer 14. The base circuit layer 14 has a plurality of first conductive pads 141. The surface of the built-up structure 15 has a plurality of second conductive pads 151.
Referring to FIG. 1C, the carrier 10 is cut along cutting edges 16 that pass through the release layers 11 such that the adhesive layers 12 around the release layers 11 are removed.
Referring to FIG. 1D, a delamination process is performed along an interface between the metal layer 13 and the release layer 11 at the top side of the carrier 10 so as to remove the carrier 10, the release layers 11 at the top and bottom sides of the carrier 10, and the metal layer 13 at the bottom side of the carrier 10.
Referring to FIG. 1E, the remaining metal layer 13 is removed.
Referring to FIG. 1F, an insulating protective layer 17 is formed on a bottom surface of the built-up structure 15 and the base circuit layer 14, and a plurality of openings 170 are formed in the insulating protective layer 17 for exposing the first conductive pads 141.
Referring to FIG. 1G, a plurality of solder balls 18a and a plurality of solder bumps 18b are formed on the first conductive pads 141 and the second conductive pads 151, respectively, thus obtaining a coreless packaging substrate.
However, since the cutting process is performed to the carrier after the built-up structure has been formed on the carrier, great stresses accumulated in the packaging substrate can easily cause warpage of the packaging substrate, thus adversely affecting the product yield. Further, the carrier cannot be repeatedly used in the same fabrication process due to the cutting process.
Therefore, how to overcome the above-described drawbacks has become critical.